Field of the Invention
The present invention relates to an image processing apparatus and an image processing method, which execute image processing using multiple image processing units.
Description of the Related Art
Heretofore, in order to improve processing performance, an image processing apparatus has been made to operate multiple function units in parallel. There have been known an image processing apparatus including one ASIC on which multiple image processing modules are mounted, configured to operate multiple image processing modules in parallel within the chip, and an image processing apparatus in which multiple image processing chips are externally connected to an external bus, configured to operate multiple chips in parallel. However, in the case of connecting the multiple chips by the bus, performance is restricted, since the transfer performance of the bus is a bottleneck. Therefore, there has been proposed an image system in which Peripheral Component Interconnect (PCI) Express (registered trademark, hereinafter referred to as PCIe) which is a high-speed serial interface for point-to-point connection is employed (see Japanese Patent Laid-Open No. 2005-323159). The image system according to Japanese Patent Laid-Open No. 2005-323159 to which multiple image processing units are connected configured to selectively operate image processing units in parallel according to details of image processing.
The image system according to Japanese Patent Laid-Open No. 2005-323159 is configured so as to connect multiple image processing modules having the PCIe interface via a device chip called as a PCIe switch. In the case of this configuration, in order to improve processing performance, the multiple image processing modules having the same function are connected to the PCIe switch to perform parallel processing. In this case, since the number of ports of the PCIe switch has to be increased corresponding to the number of processing modules to be increased, the circuit scale and the number of terminals of the PCIe switch chip are increased in proportion to the number of the ports.
Also, Japanese Patent Laid-Open No. 2005-323159 discloses an example in which image data equivalent to one page is divided in the main scanning direction using the multiple image processing modules, and the image data is processed in parallel at each processing module in a distributed manner. However, in the case of diving image processing using such a method, upon the number of the processing modules being increased for handling high speed, since the number of divisions in the main scanning direction is also increased, a dividing method of input image data, and a coupling method for the image data after processing are complicated.